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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCDEVARCH, Device Architecture Register</h1><p>The TRCDEVARCH characteristics are:</p><h2>Purpose</h2>
        <p>Provides discovery information for the component.</p>

      
        <p>For additional information, see the CoreSight Architecture Specification.</p>
      <h2>Configuration</h2><p>External register TRCDEVARCH bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-trcdevarch.html">TRCDEVARCH[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCDEVARCH are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRCDEVARCH is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="11"><a href="#fieldset_0-31_21">ARCHITECT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">PRESENT</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">REVISION</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">ARCHVER</a></td><td class="lr" colspan="12"><a href="#fieldset_0-11_0">ARCHPART</a></td></tr></tbody></table><h4 id="fieldset_0-31_21">ARCHITECT, bits [31:21]</h4><div class="field">
      <p>Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.</p>
    <table class="valuetable"><tr><th>ARCHITECT</th><th>Meaning</th></tr><tr><td class="bitfield">0b01000111011</td><td>
          <p>JEP106 continuation code <span class="hexnumber">0x4</span>, ID code <span class="hexnumber">0x3B</span>.</p>
        </td></tr></table><p>Other values are defined by the JEDEC JEP106 standard.</p>
<p>This field reads as <span class="hexnumber">0x23B</span>.</p></div><h4 id="fieldset_0-20_20">PRESENT, bit [20]</h4><div class="field">
      <p>DEVARCH Present. Defines that the DEVARCH register is present.</p>
    <table class="valuetable"><tr><th>PRESENT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Device Architecture information not present.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Device Architecture information present.</p>
        </td></tr></table>
      <p>This field reads as 1.</p>
    </div><h4 id="fieldset_0-19_16">REVISION, bits [19:16]</h4><div class="field">
      <p>Revision. Defines the architecture revision of the component. Defined values are:</p>
    <table class="valuetable"><tr><th>REVISION</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>ETEv1.0, <span class="xref">FEAT_ETE</span>.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>ETEv1.1, <span class="xref">FEAT_ETEv1p1</span>.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>ETEv1.2, <span class="xref">FEAT_ETEv1p2</span>.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>ETEv1.3, <span class="xref">FEAT_ETEv1p3</span>.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-15_12">ARCHVER, bits [15:12]</h4><div class="field">
      <p>Architecture Version. Defines the architecture version of the component.</p>
    <table class="valuetable"><tr><th>ARCHVER</th><th>Meaning</th></tr><tr><td class="bitfield">0b0101</td><td>
          <p>ETEv1.</p>
        </td></tr></table><p>ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].</p>
<p>This field reads as <span class="hexnumber">0x5</span>.</p></div><h4 id="fieldset_0-11_0">ARCHPART, bits [11:0]</h4><div class="field">
      <p>Architecture Part. Defines the architecture of the component.</p>
    <table class="valuetable"><tr><th>ARCHPART</th><th>Meaning</th></tr><tr><td class="bitfield">0xA13</td><td>
          <p>Arm PE trace architecture.</p>
        </td></tr></table><p>ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].</p>
<p>This field reads as <span class="hexnumber">0xA13</span>.</p></div><h2>Accessing TRCDEVARCH</h2>
        <p>External debugger accesses to this register are unaffected by the OS Lock.</p>
      <h4>TRCDEVARCH can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>ETE</td><td><span class="hexnumber">0xFBC</span></td><td>TRCDEVARCH</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When !IsTraceCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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